- Design & verification of hardware IPs
- Design & verification methodology study
- Work with senior engineers to improve PPA of HW design.
- Create automation flow to improve engineering efficiency
- Master candidate in EE/CS or related field
- Basic C/C++ knowledge is a must
- Basic digital circuit/verilog knowledge is a must
- Quick learner, willing to take challenges in a new field
- Fluent English and good communication skills
- Scripting knowledge (Perl/Python/Shell) is a plus
- High level synthesis knowledge is a plus
- Video/image/CV processing background is a plus
- Microprocessor/security background is a plus
- Deep learning background is a plus
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ASIC Design Intern - Shanghai, 中国 - NVIDIA
描述
We are now looking for ASIC Design Interns
NVIDIA MMPLEX team is in Shanghai with more than 300 team members. We deliver cutting-edge IP solutions to multiple NVIDIA product lines, for example: datacenter, GeForce, automotive, networking etc. Our IPs include micro-processor, security, DL/CV accelerators, display, video encoder/decoder, image processor etc. We are looking to grow our teams with the smartest people in the world, join us if you want to learn about world's leading IP technology and development process.
What you'll be doing:
What we need to see:
Ways to stand out from the crowd:
