Senior Design Verification Engineer - Shanghai
1周前
Job summary
本科及以上学历电子、计算机等理工科专业深刻理解IC验证流程具备IP/子系统验证经验熟悉SystemVerilog,UVM验证方法学和SVA掌握一种或几种脚本语言如perl/python/makefile 等有NAND子系统设计和验证经验者优先具有固件/硬件联合仿真经验者优先具备团队合作精神较强逻辑分析能力沟通协调能力强工作认真负责求知欲强愿意接受挑战
- 参与前沿存储芯片的验证开发
- 基于UVM开发可重用的测试平台以及针对IP/子系统的随机和定向测试用例
职位描述
, consectetur adipiscing elit. Nullam tempor vestibulum ex, eget consequat quam pellentesque vel. Etiam congue sed elit nec elementum. Morbi diam metus, rutrum id eleifend ac, porta in lectus. Sed scelerisque a augue et ornare.
Donec lacinia nisi nec odio ultricies imperdiet.
Morbi a dolor dignissim, tristique enim et, semper lacus. Morbi laoreet sollicitudin justo eget eleifend. Donec felis augue, accumsan in dapibus a, mattis sed ligula.
Vestibulum at aliquet erat. Curabitur rhoncus urna vitae quam suscipit
, at pulvinar turpis lacinia. Mauris magna sem, dignissim finibus fermentum ac, placerat at ex. Pellentesque aliquet, lorem pulvinar mollis ornare, orci turpis fermentum urna, non ullamcorper ligula enim a ante. Duis dolor est, consectetur ut sapien lacinia, tempor condimentum purus.
访问所有高级职位，获得理想工作。
类似职位
As chip sizes continue to grow power efficiency has become critical across all NVIDIA products - from data centers to automotive and personal computing. · BS with 4+ years of experience or MS with 2+ years of working experience. · Solid IC background. · ...
We are seeking a Principal Verification Engineer to join our team in Shanghai. The successful candidate will have a highly visible role in product development and take ownership of defining and executing verification plans for exciting DDR memory interface products. · ...
As a Principal Verification Engineer the candidate will be reporting to the Director of Verification in this Full-Time position. Successful applicants will have a highly visible role in product development and take ownership of defining and executing verification plans for exciti ...
As a Principal Verification Engineer the candidate will be reporting to the Director of Verification in this Full-Time position. · ...
Design verification engineer for control fabric IP team at AMD in Shanghai. · Develop comprehensive block level verification test plan for DUT. · Develop testbench and test cases with SystemVerilog/UVM/Formal verification methodologies. · Support Subsystem and SOC level verificat ...
The focus of this role is to plan, build, and execute the verification of new and existing features for AMD's GPU · and Memory System IP. · ...
As chip sizes continue to grow power efficiency has become critical across all NVIDIA products from data centers to automotive and personal computing Our PMU IP developed over the past 17 years is crucial in optimizing chip performance and efficiency in both idle and active scena ...
We are seeking a Senior Verification Engineer to join our Power Management Unit (PMU) IP team to help building more powerful PMU engine. · ...
We are seeking a Senior Verification Engineer to join our Power Management Unit (PMU) IP team. · We require senior verification engineer for power management unit ip generation, · a strong background in ic design encompassing verilog,vhdl,c,c++,systemverilog,uvm ,perl python scri ...
该职位来源于猎聘 岗位职责 1.产品测试与验证:负责 BE/BH/SE 等系列 400G/800G 产品的 AEC Cable、PCB、EVB 测试和验证工作,以及 Seagull/Dove/Lark 系列 200G/400G/800G 光模块的全面验证,确保产品性能符合行业标准及客户需求。 · 硬件与芯片验证:开展板级硬件和芯片产品的验证工作,对硬件 EVB、芯片、AEC 部分进行深入测试 · ...
The Role · Control Fabric (CF) IP is the backbone of AMD SOCs. · We design and deliver cutting-edge technologies of network-on-chip (NoC), chiplet interconnect, · remote system management unit, advanced power & thermal management, clocking etc. ...
硬件验证工程师负责产品测试与验证、硬件与芯片验证以及脚本开发与优化。 任职要求包括电子信息通信工程或光电工程专业本科及以上学历,熟悉400G/800G光模块及AEC Cable PCB EVB的测试流程标准,掌握板级硬件和芯片产品的验证方法等。 ...
产品测试与验证:负责BE/BH/SE等系列400G/800G产品的AEC Cable、PCB、EVB测试和验证工作 · 硬件与芯片验证:开展板级硬件和芯片产品的验证工作 · ...
We are now looking for Chip Design Engineer for the Switch Silicon group to design and implement state-of-the-art Switch Silicon chips. · ...
We are now looking for Chip Design Engineer for the Switch Silicon group. As a Chip Design Engineer at NVIDIA's Networking business unit, you'll join a group of passionate engineers to design and implement the next generation state of the art Switch Silicon chips.Work in a combin ...
NVIDIA MMPLEX team delivers cutting-edge IP solutions with over 300 team members in Shanghai. · Participate in verification methodology research to improve automation and productivity. · Read IAS and design specs to understand design requirement and build corresponding testplan. ...
NVIDIA is hiring a verification engineer to work with Arch, design and verification engineers to verify control units and silicon measurement related units from unit-level to fullchip-level. · ...
+ NVIDIA SOC System-ASIC team is hiring a verification engineer. · + Micro-architecture definition for System-level modules (Fuse, Strap, Floorsweep, In-silicon measurement, Reset, Sysctrl) · Unit-level and System-level verification for System-level modules. · ...
As a Senior Principal Verification Engineer the candidate will be reporting to the Director of Verification in this Full-Time position. · ...
NVIDIA MMPLEX team is dedicated to delivering cutting-edge IP solutions to various NVIDIA product lines. · BS / MS in electrical / computer engineering or equivalent experience. · 3+ years (MS) or 5+ years (BS) working experience. · ...