Description:

岗位描述：

The candidate is expected to be responsible for following tasks:
- Participate in complex Chip DFT/DFD feature and architecture definition
- Implement DFT function including SCAN, Boundary SCAN, MBIST, Analog Macro test logic
- Generate DFT related timing constraints and work for timing closure
- Develop and verify high coverage and cost effective test patterns for the production test
- Design, implement and verify other DFX (debug, characterization, yield etc) feature
- Evaluate and establish the advanced DFT/DFD tools and flow

岗位要求：

6+ years for Bachelor or 3+ years for master degree experience in DFT design and verification, test pattern development

KEY KNOWLEDGE, SKILLS AND ABBILITIES REQUIRED
- Good Knowledge of Scan/ATPG, MBIST and boundary scan and other DFT techniques
- Good Knowledge of industry DFT tools like DFTMax, TetraMax ,TestKompress, FastScan, Tessent Mbist, SMS etc
- Good knowledge of digital SoC/ASIC design, including STA, verification and RTL coding
- Proficient in hardware description languages such as Verilog, System Verilog and VHDL
- Good Knowledge of script language, such as Tcl, Python, Perl
- Good English hearing, speaking, reading and writing capabilities
- Strong commitment to schedule and work quality, good team player

我们鼓励人人践行公益，同学如参与过公益活动，有相关证明，也欢迎附在简历中。参考依据包括但不限于：全国志愿服务信息系统开具的志愿服务证明、“人人3小时”公益平台公益时证书、志愿服务组织（含社会团体、社会服务机构、基金会）授予的志愿服务证明等。